The disclosed embodiments of the present invention relate to video encoding/decoding, and more particularly, to a video processing system with shared/configurable in-loop filter data buffer architecture and related video processing method thereof.
In the H.264 standard, a de-blocking filter (DF) placed in the prediction loop is one important tool to increase the coding efficiency and remove the blocking artifacts. For example, the DF process is invoked with four samples of each side of macroblock boundary for luminance component and two samples of each side of macroblock boundary for chrominance component. Therefore, at least four line buffers are required for the luminance component and two line buffers are required for the chrominance component, respectively.
In the high efficiency video coding (HEVC) standard, a de-blocking filter may be implemented with picture-based processing, which needs a whole picture buffer to store pixel samples before in-loop filter process.
Hence, as the DF processes of the H.264 codec system and the DF process of the HEVC codec system have respective data buffer requirements, and the HEVC de-blocking filter may be implemented with picture-based processing, the production cost of a video codec chip which supports both of the H.264 standard and the HEVC standard would be very high.